1. Field
Example embodiments relate to field effect transistors (FETs), for example, to FETs and methods for manufacturing FETs.
2. Description of the Related Art
As the integration density of integrated circuit field effect transistors (FETs) continues to increase, the size of the active region and the channel length may continue to decrease. With the reduction in the channel length of the transistor, the influence of the source and/or drain upon the electric field or potential in the channel region may increase. This is called the “short channel effect”. Further, scaling down the active size may include decreasing the channel width, which may increase a threshold voltage. This is called the “narrow width effect”.
Various structures have been developed to improve or maximize the device performance, while reducing the sizes of elements formed on a substrate. For example, a fin FET (FinFET) transistor has been proposed and is in use today for memory devices. However, conventional FinFETs may also have problems. FinFETs may have a higher off current, because of a shorter distance (effective length) between source and drain. Also, FinFETs may have a stronger GIDL (Gate-Induced Leakage) problem.
FIG. 1 illustrates a relationship between a conventional gate structure 26 and a conventional source/drain 30. As shown in FIG. 1, the gate structure 26 may be formed between the source/drain 30. As the size of the transistor of FIG. 1 is reduced, the effective length (EL) between the source and drain is reduced, therefore the GIDL and/or off current may be increased.